AVR interrupt priority

Single chip microcomputer STM32L151CCU6

EL-C1600N100013-B

1206RGB (single)

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In the same priority level of the AVR microcontroller, the lower the interrupt vector entry address, the higher its priority. After responding to the interrupt, the AVR microcontroller will disable the system from responding to the remaining interrupts. If the program needs to respond to other interrupt events in an interrupt service routine, you can re-enable the global interrupt with the SEI instruction or _SEI()(IAR), SEI()(ICCAVR) in the interrupt service routine. Otherwise, the AVR microcontroller will only re-enable the global interrupt when it exits the interrupt process.

AVR (at least ATmega16) microcontrollers use a fixed hardware priority mode and do not support software resetting of interrupt priority.

AVR has different interrupt sources. Each interrupt and reset has an independent interrupt vector in program space. All interrupt events have their own enable bits. An interrupt can occur when the enable bit is set and the global interrupt enable bit I of the status register is also set. Depending on the program counter PC, the interrupt may be automatically disabled if the boot lock bit BLB02 or BLB12 is programmed. This feature improves the security of the software. See the description of P247 "Memory Programming" for details.

The lowest address of the program memory area defaults to the reset vector and the interrupt vector. See P43 "Interrupts" for a complete list of vectors. The list also determines the priority of the different interrupts. The lower the address where the vector is located, the higher the priority. RESET has the highest priority and the second is INT0 – External Interrupt Request 0. The interrupt vector can be moved to the beginning of the boot Flash by setting the IVSEL of the MCU Control Register (MCUCR). The programming fuse bit BOOTRST can also move the reset vector to the beginning of the boot flash. See P234 "Support Boot Loader - Read (WW, Read-While-Write) self-programming capability while writing".

The global interrupt enable bit, I, is cleared when any interrupt occurs, thus disabling all other interrupts. User software can set interrupts in the interrupt routine to implement interrupt nesting. At this point all interrupts can interrupt the current interrupt service routine. I is automatically set after the RETI instruction is executed.

There are basically two types of interruptions. The first is triggered by an event and sets the interrupt flag. For these interrupts, the program counter branches to the actual interrupt vector to execute the interrupt handler, and the hardware clears the corresponding interrupt flag. The interrupt flag can also be cleared by writing "1" to it. When an interrupt occurs, if the corresponding interrupt enable bit is "0", the interrupt flag bit is set and remains until the interrupt is executed or cleared by software. Similarly, if the global interrupt flag is cleared, all interrupts that have occurred will not be executed until I is set. The pending interrupts are then executed in order of interrupt priority.

The second type of interrupt is triggered as long as the interrupt condition is met. These interrupts do not require an interrupt flag. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

After the AVR exits the interrupt, it always returns to the main program and executes at least one instruction to execute other suspended interrupts. It should be noted that the status register is not automatically saved when entering the interrupt service routine, and will not be automatically restored when the interrupt returns. This work must be done by the user through software.

When the interrupt is disabled using the CLI instruction, the interrupt disable takes effect immediately. No interrupt can occur after executing a CLI instruction, even if it is happening while executing a CLI instruction.