Small Adjustable Output Voltage Amplitude Inverter Design

Inverters are electrical devices that convert steam energy into alternating current power and are typically implemented with high power, high backpressure power electronics. In solar power generation, the electricity generated by the photovoltaic array is direct current. However, the power supply for most of the electrical equipment is AC power, so power systems often require inverters that convert DC power into AC power. In addition, inverters are also widely used in industrial control, communications and transportation. Sinusoidal Pulse Width Modulation (SPWM) means that a sinusoidal wave is used as a modulating wave, and a triangular wave with a frequency of F times the frequency of a sinusoidal wave is used as a carrier wave to generate a waveform after comparison. A set of rectangular pulse sequences with equal amplitude and proportional to the sinusoidal modulated wave is equivalent to a sinusoidal modulated wave. This paper takes the STC12C5A60S microcontroller as the core, uses its internal two programmable count array (PCA) module to simulate the pulse width modulation method, and designs and implements a small inverter with adjustable output voltage amplitude.

This article uses AlTIumDesigner6.9 to complete the hardware circuit schematic and PCB diagram design. Figure 1 shows the overall circuit configuration of this design.

The function achieved by this design is to use a three-level power conversion (DC-HFAC-DC-LFAC) to obtain a 6 V DC power line with a frequency of 50 Hz and an amplitude of 110 V for AC load. The specific design and function of each part of the hardware circuit are described as follows.

1.1 Power Module

Using a DC-to-DC conversion chip MC34063 in combination with the LM7805 and LM7812 to obtain DC currents of 12 V and 5 V, providing the required power for each module of the hardware circuit.

1.2 Foreline boost module

Through the SG3525 chip and its peripheral circuits to generate two complementary high-frequency PWM (Pulse Width ModulaTIon) pulse wave, with the two high-frequency pulse wave to control the unilateral bridge composed of two MOS (IRF 3205) composed of high-frequency inverter , and with the high-frequency transformer together to achieve the previous step boost. Through the boost of the preceding stage, the 6 V DC is raised to a high-frequency AC of about 300 V to prepare for the inversion of the power frequency.

1.3 Rectifiers and Filtering Modules

Four diodes form a rectifier bridge circuit to rectify the high-frequency alternating current output from the boosting module of the preceding stage, and are filtered by the LC filter as the input of the industrial frequency inverter bridge circuit.

1.4 Power Frequency Inverter MOS Bridge Circuit Driver Module

In this design, the four MOS transistors driving the power frequency inverter bridge are implemented using the IR2110 chip. The two-way SPWM control signal generated by the single-chip microcomputer is used as the logic input of two IR2110s after the dead time. The driver circuit composed of two IR2110 chips outputs four pairs of complementary signals so as to control the on-off of the upper and lower bridges of the full-bridge inverter circuit to realize the inverter function.

1.5 SPWM Generation Module

The minimum system built with the STC12C5A60S microcontroller as the core is used as the control part of the module. At the same time, an analog/digital conversion circuit is added. By reading the voltage value on the potentiometer, the output amplitude of the inverter can be adjusted. The two-way SPWM signal is the output port P1.3 and P1.4 of the PCA module of the STC12C5A60S microcontroller. The principle is to use the sine table data to set the value of the compare register of the PCA module of the STC12C5A60S microcontroller to simulate the pulse width modulation method. Finally, a rectangular pulse sequence whose width is proportional to the sine wave is obtained to generate the equivalent sine wave. The principle of generating two SPWM waves is shown in Figure 2.

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