Main fault analysis of sequential logic circuits
The output of the sequential logic circuit at any one time depends not only on the input at that time, but also on the input at each moment in the past. Common sequential logic circuits include flip-flops, counters, registers, and so on. Since the sequential logic circuit has the function of storage or memory, it is complicated to overhaul.
Main fault analysis of digital circuits with sequential logic circuits:
1. Clock: The clock is the synchronization signal of the entire system. When the clock fails, it will bring about the overall malfunction. Loss of clock pulses can cause the system data bus, address bus, or control bus to be inactive. Changes in the rate, amplitude, width, shape, and phase of the clock pulse can cause failures.
2. Reset: Devices containing microprocessors (MPUs), even with minimal systems, typically have a reset function. The reset pulse is loaded onto the MPU when the system is powered up, or the program is returned to its original state under certain conditions (for example, the watchdog Watchdog program). When the reset pulse cannot occur, the signal is too narrow, the signal amplitude is incorrect, there is interference in the conversion, or the conversion is too slow, the program may start at the wrong address, causing program confusion.
3. Bus: The bus transfers the instruction series and control events, which generally have an address bus, a data bus, and a control bus. When the bus has an error even if there is only one bit, it will seriously affect the system function, error addressing, error data or error operation. Bus errors can occur in the bus driver or in other components that receive data bits.
4. Interrupts: Systems with microprocessors (MPUs) are generally capable of responding to interrupt signals or device requests, generating control logic to temporarily interrupt program execution, go to a special program, service the interrupt device, and then automatically return to the main program. The interrupt error is mainly interrupted line sticking (the system is operating very slowly at this time) or interfered with (system error response interrupt request).
5. Signal Attenuation and Distortion: Long parallel bus and control lines may experience crosstalk and transmission line failure, as a result of spikes (interactive crosstalk) on adjacent signal lines or ringing on the drive line (equivalent to logic) Multiple conversions of the level), which may add erroneous data or control signals. There are many possible reasons for signal attenuation, such as high humidity environment, long transmission line, and high rate conversion. Large electronic interference sources can cause electromagnetic interference (EMI), which causes signal distortion and causes dysfunction of the circuit.
The sequential logic circuit means that the output state at any time is not only related to the state of the input signal at that moment, but also to the state of the circuit before the signal is applied. Therefore, in the circuit structure, a memory circuit having a memory function must be included.
The analysis of the sequential logic circuit refers to the process of giving a logic diagram of the sequential circuit and solving the logic function of the circuit. The general analysis methods and steps of the synchronous sequential circuit are shown in the figure below.
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