Introduction to the basic concepts of setup and hold timing analysis
The timing analysis concepts we will introduce today are setup and hold. These two concepts are certainly familiar to you, and this is the two most basic timing analysis. We see the timing report of setup and hold every day. Have you ever wondered why we need to do setup and hold analysis?
The figure above is a brief schematic of a trigger. Among them, T1, T2, T3, and T4 are all transmission gates, and they are all level-sensitive. The so-called clock transitions can be interpreted as high-level and low-level mutual transitions. T1 and T4 are on at the same time, T2 and T3 are on at the same time, and the conduction states of T1, T4 and T2 and T3 are mutually inverted. The delay of the actual unit in the circuit is mainly due to the time spent through the electronic device when the electrical signal is turned on.
How does that trigger work?
When it is low, T1 and T4 are turned on. At this time, the data enters `D, because T4 is turned on at this time. Since a pair of inverters form a bistable structure, the data in the green arrow line in the figure is kept on a beat. Data results.
When the high level arrives, T1 and T4 turn off, and T2 and T3 turn on. The bistable structure guarantees that the data in 2 remains stable and is output to the Q terminal through T3. At the same time, the data at points B and C remain consistent and stable; When the low level arrives, T2 and T3 are turned off, and T1 and T4 are turned on, because the data at points B and C are always stable. Therefore, it can be ensured that the green arrow lines have stable and consistent data to be sent out through the Q terminal. Therefore, it can be seen that the data sampled on the rising edge can be held for one clock cycle.
Setup time (Tsu): The time that input data D must be valid before the rising edge of the clock. In order to obtain effective data, it must be ensured that the data at points A and D are consistent and stable. Therefore, it can be understood that the so-called set-up time refers to how long the input data D will take to make the data of `D stable and reliable. So the setup time refers to the time the data reaches D from D.
Hold time (Thold): we can imagine that after the rising edge of the clock, if the data of point A is affected by point D, resulting in inconsistent data of points A and D, that is, after the rising edge occurred, that is, T2, When T3 is on, the data circulating in 2 cannot be kept stable, resulting in unstable Q-end data. Therefore, the hold time can be understood as that the data at the D end passes through T1, and then passes through 2 to reach the point A. This ensures that the data of A and D are consistent and stable.
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