LDO power management system design principle

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Overview:
In order to solve the problem that the cost and area of ​​the board increase due to the common single chip of the LDO power supply module in the power carrier communication system. In this paper, the LDO is integrated into the system chip to supply power to the digital and analog modules respectively. At the same time, the smooth pole follow-up technology is used to solve the chip stability problem when the load current changes. This method can make the PSRR reach 63 dB at low frequency and can be IP-based. Used in other applications.

0 Introduction Power management system has become a hot spot in the development of the current integrated circuit industry, and is also an indispensable technology. Without power management, many markets will not exist. Power management can make many markets, such as mobile phones, laptops, remote-controlled TVs, and reliable telephone services, a reality. Nowadays, electronic products have been popularized in all aspects of work and life. Their performance and price ratio are getting higher and higher, and the functions are getting stronger and stronger. The power supply circuit is also more and more important in the whole circuit.
Unreasonable power system design will affect the architecture of the entire system, product characteristics, component selection, software design and power distribution architecture. How to ensure the stability of LDO under different current loads is a challenge to the design of LDO. To this end, an LDO is proposed in this paper, and the smooth pole following technique is used to solve the stability problem caused by the pole offset under different current loads, thereby improving the PSRR. At the same time, the overvoltage protection circuit is also better prevented. LDO output power supply voltage is too large.

1 Circuit Design Figure 1 shows the circuit structure of the LDO in this design. The basic structure of the LDO consists of four stages, and the negative feedback loop formed by the error amplifier A1, the voltage amplifier A2, the voltage buffer A3, the voltage adjustment tube MP1, and the feedback network is mainly used to maintain the stability of VOUT. The Miller capacitor C1 is used to compensate the frequency of the circuit. The bandwidth of the second and third stages is large to ensure that the LDO is in a stable state. Also should be guaranteed in a wider

For an internal gain-compensated high-gain system, Miller compensation is better able to control its stability over a larger range of load capacitances, while also providing a better transient response. Because a high frequency negative feedback formed by Miller capacitance can be directly coupled to the output, high gain can achieve better DC and load modulation. However, the test results show that the LDO will have an adjustment of about 50 mV when the load current changes greatly. This is because the performance of the DC load modulation is limited by the parasitic capacitance of the bonding wire, which directly degrades the DC load modulation by the parasitic capacitance of the DC.
The output current of the LDO is required from 0 to full load (100mA in this design), so gm4 will also vary with load current, causing the secondary point P2 to also change with load current. The design can be solved by smooth pole technology. For circuits composed of R and MP2 series, it can be dynamically biased according to the change of load current. Under high load current conditions, R and MP2 can bias a larger current to broaden the circuit bandwidth while reducing the output resistance to accommodate the secondary point P2 being pushed to a higher frequency. At low load currents, P2 is at a lower frequency and biases R and MP2 to a narrower bandwidth and larger resistance to ensure stability. The static bias current should be as small as possible to ensure low power consumption of the circuit.
The gate of the trim tube can be designed such that the resistance to ground is significantly greater than the resistance to VDD, so that the gate of the trim tube can follow the change in the power supply, resulting in better power supply rejection. To generate a small resistance to VDD, R and M can be connected in series between the gate and VDD. If the load current of the LDO is small, then the trim tube will operate in the weak anti- or sub-threshold region. Therefore, the Vcs of the MP is less than Vth. Since the Vcs of the MP and MP are equal, the MP is turned off. In this case, R is biased by the N-tube of the pre-stage circuit. When the load current of the LDO is large, the Vcs of the adjustment tube is increased, the MP is turned on, and the R is connected in series with a small resistance, and the MP acts as a switch. At this time, the resistance of the regulator tube gate to VDD is greatly reduced, and the front-stage bias current is increased, and the bandwidth is also increased. In terms of loop stability, it allows the LDO to adapt to changes in load current by dynamically changing the bandwidth and resistance at the gate of the tube to better improve the transient response of the circuit.
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