FPGA application tips and tips (1): FPGA debounce things

code show as below:

Program analysis:

Debounce

Debounce can be divided into hardware debounce and software debounce. As the name suggests, hardware debounce is the purpose of debounce through hardware. It is generally implemented by Schmitt trigger, which consumes hardware resources. In some cost constraints, Software is often used to shake.

The principle of software debounce: the jitter frequency of the general button is several tens of khz (so the state transition interval is ms level, we use 20ms in the program). The overall idea is to skip this segment of jitter. The debounce state machine we designed is as follows:

If the button is low when pressed, idle is the initial state. When a button is pressed, key_pre==0, and the delay1 state is entered. (Note: the state takes 20ms from idle to delay1, which is equivalent to skipping jitter). If the key_pre is still 0 at this time, we think that the button is pressed, then it will enter the next state, otherwise it will return to the jitter when it is considered to be jittery. In the press state, if the key is raised, ie key_pre==1, the delay2 state is entered, otherwise it is still in the press state (preventing a long press), in the delay2 state, if the key_pre is still 1, the button is considered Lift up, then enter the next state taiqi, and then complete the lifting and debounce, you can generate the signal after debounce.

Program key points:

First: the generation of delay signal

The high time of the delay signal is only the width of a master clock, so when delay==1, the state transition alv block will only trigger once, not multiple times.

Second: the generation of the signal key_out after debounce (output high level means press).

We use in the program

Assign key_out=(state==taiqi && delay==1)?1'b1:1'b0;

Some people think that when the state is taiqi, it can be output directly. Why is there a delay==1 condition? Let's take a look at the two simulation results:

Plus delay==1

From the figure we can clearly see that without delay ==1, key_out is 1 with a wide pulse width. In the case of clk_50M as a sensitive signal, it will cause multiple triggers, plus delay==1, key_out The width is only one clk_50M main clock width, which achieves the debounce effect.

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