This blog wants to figure out what the whole process of program booting and booting after FPGA power-on configuration is not about how to write a bootloader.
Subject extraction I created an embedded system based on MicroBlaze (similar to the one shown in Figure 1, of course not as complicated as Figure 1). The on-chip BRAM is only 64KB, and the program image generated by me is more than 2MB, so in this case, the program image cannot be directly configured into the on-chip BRAM with the bit stream file used to configure the FPGA. The solution is to use an external non-volatile storage medium to store program images and bit stream files, such as PROM, or Flash. Xilinx provides a SystemACE configuration solution, so what about the entire workflow? [[wysiwyg_imageupload:290:]]
Figure 1. MicroBlaze-based SOPC architecture
In Reference 1, there is a saying that the SystemACE solution downloads the program to debug via JTAG (for MicroBlaze, the MicroBlaze debug module). Seeing this sentence, I didn’t react at the moment. Be aware that the SystemACE solution combines the bitsteams file used to configure the FPGA with the program executable binaries to generate a *.ace. After reading genace.tcl, the script used to generate the ace file, I finally understood the sentence just mentioned.
First explain how the SystemACE file is generated?
1. Convert the bitstream file to an SVF file via the iMPACT tool. The SVF file contains the JTAG instruction sequence for configuring the FPGA.
2. Convert the elf executable file to an SVF file via XMD. The SVF file contains the JTAG instruction sequence for downloading the ELF file with memory or on-chip BRAM via XMD.
3. Convert data/binary code to SVF file via XMD
4. Link the SVF files generated in the first and second steps
5. Using the iMPACT tool to generate the systemACE file using the combined SVF file The entire generation process is clear. The SystemACE solution replaces the process of such an online debugging: download the bitstream file of the program containing the bootloop to the FPGA through JTAG through iMPACT. In the idle, waiting for the running of the program to load. Next, through XMD, first communicate with debug and CPU, then download the program to the specified memory or BRAM, and then run the CPU.
In summary, the SystemACE configuration solution requires hardware support, namely SystemACE controller and CF card. Of course, the Debug module needs to be added in the embedded system. The advantages are obvious, there is no need to write a bootload-like bootloader, and you don't need to care about the size of the program image, because the CF card has a large capacity and meets the requirements of most embedded applications.
Another situation is to configure the FPGA through the PROM/FLASH storage program image and the bitstream file, and boot the program. The specific process is as follows:
I don't care how to configure the FPGA here, but I care about how the system boots. Take the example of running Linux on an FPGA. As shown in Figure 3, the specific steps are as follows:
In the first step, the CPU executes Loader1 from the 0x0 address (BRAM) (note that Loader1 is placed in BRAM and is added during FPGA configuration)
In the second step, Loader1 reads the Loader2 program in SPI Flash and then copies it into memory.
The third step, the Loader1 program jumps to execute Loader2 in memory.
The fourth step, Loader2 reads the compressed kernel image in SPI Flash, the fifth step, the Loader2 program decompresses the kernel to another memory space, the sixth step, the Loader2 program jumps to the decompressed kernel image, the seventh step, the Linux kernel starts from above. The process knows that if you configure it through PROM or Flash, you need Bootload support, that is, you need to finish reading the program image from the Flash or PROM to the memory. Of course, you need to add a PROM or Flash controller in the embedded system.
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