Recently I am preparing to find a job. Because it is doing FPGA development, verilog realizes the technology frequency division circuit is a frequently-occurring problem, three-way, five-way circuit, etc.
After an afternoon of summing up a general-purpose circuit, any odd-numbered frequency dividing circuit can be realized.
The verilog code is as follows:
Module fenpin3(clk,clkout,rst);//odd frequency divider circuit capable of 3,5,7 division
Input clk,rst;
Output clkout;
Reg [2:0] a,b;
Reg clkout;
Parameter fenpin=3;
Always@(posedge clk or negedge rst)
Begin
If(!rst)
a<=0;
Else if(a==fenpin-1)
a<=0;
Else
a<=a+1;
End
Always@(negedge clk or negedge rst)
Begin
If(!rst)
b<=0;
Else if(b==fenpin-1)
b<=0;
Else
b<=b+1;
End
Always@(a or b or rst)
Begin
If(!rst)
Clkout<=0;
Else if((a+b==1)||(a+b==fenpin+1))
Clkout<=~clkout;
End
Endmodule
Through the above circuit, a circuit with an arbitrary duty ratio of 1/2 can be realized. The simulation waveform is as follows:
Three-way:
Five-way:
Seventh frequency:
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